Technical Brief: HCI & NBTI Reliability Impact on Submicron IC Design
Reliability related IC issues have existed for decades as many papers presented at IRPS
(International Reliability Process Symposium) Conferences for many years can attest.
However, until now, HCI (Hot Carrier Injection) & NBTI (Negative Bias Thermal Instability)
issues have not had a significant enough impact on designs due to the larger geometry IC
processes of days past. For designs that are now using 0.13 micron or below processes, some
design teams have been finding out the hard way that they should have done HCI & NBTI analysis
to ensure they can deliver maximum performance chips. Additionally, since these IC processes
will become mainstream in 2002, NBTI reliability analysis has become a key issue to address.
However, those currently doing high performance designs or those with high reliability requirements
will need to address these issues now. Identifying reliability related performance problems earlier
in design process means faster and more reliable end products with vastly reduced chip re-spins,
wasted silicon and potentially millions of dollars in mask tooling and problematic first silicon.
Who Needs to be Concerned About Reliability Related Degradation?
HCI & NBTI reliability issues must be addressed by any designer who is pushing for highest performance
IC's with 0.13 micron or below geometry process technologies that use thermal nitrides for the gate
insulator. This specifically includes foundries, Integrated Device Manufacturers ("IDM") and those
fabless houses, which have control over their IC processes. Additionally, fabless design companies,
-- even those using standard libraries -- in an effort to maximize performance of their high end ASIC
or SoC, will need to address reliability induced degradation. For fabless designers using standard
libraries, the designer will need to work together with their foundry resource in establishing library
data and software that can work with this data to address reliability induced problems.
It is a Performance Issue More Than Reliability
HCI & NBTI related problems are mainly performance problems more so than failure or "reliability" itself.
The traditional "DC Stress" tests now result in such short DC lifetimes that designers can no longer trust
these DC tests as a true measure of realistic AC lifetimes. Without quantifiable reliability design solutions
in place, designers will either sacrifice performance due to the over margining that is typically done by
designing to artificially pessimistic corner cases or they will have excessive burn-in failures - all very
late in the design process. Certainly, for those with critical reliability needs, such as implanted medical
devices, aerospace or other safety critical applications, reliability is a key concern in order to avoid in
the field failures. However, the most significant impacts caused by reliability issues are reduced design
performance, design delays, chip re-spin costs and lost time to market. Numerous studies have proven how much
more value an IC can warrant in the market by having extra performance in those devices sold to the market
earlier rather than later.
About Hot-Carrier Injection ("HCI") Induced Degradation
HCI degradation slows down circuit speeds that can potentially cause circuit-operating failures.
HCI arises as a result of the aggressive scaling of device geometries, most notably for short device
channel lengths. Shorter channel lengths mean higher circuit speeds, but they also increase electric
fields in the channel. These fields can damage the gate oxide interface, resulting in degradation in device
performance. The amount of device degradation is not constant for each device, but is a function of the
device's unique switching activity within each circuit. In the past, designers had no means of uncovering
such specific information.
About Negative Bias Temperature Instability ("NBTI")
NBTI degradation is critical for chip processes using thermal nitride gate insulators - which are now at such
thicknesses that NBTI effects can prevent a chip designer from relying on the expected performance of the
process. Unlike HCI, NBTI is not exclusively for short channel devices as it is directly related to the
process shrinks in the vertical geometries. Like HCI, the amount of device degradation is not constant for
each device, but is a function of the device's unique switching activity within each circuit. Additionally,
for devices that are subject to high temperature application conditions, whether due to the chip's own heat
dissipation or the environment it is to be used in, NBTI failures will occur in the field independent of those
found during burn-in testing. In the past, designers had no means of uncovering such specific information
other than using artificial DC stress tests and reduced yield from high temperature burn-in failures or by
designing all parts of the chip to the absolute worst-case corner conditions. An NBTI design solution will
help a designer identify where problems might exist so the designer can design around situations such as
voltage overshoot, as well as other conditions a designer can compensate for without sacrificing performance.
Designing without Reliability Design Solutions
Without any reliability modeling or simulation, a designer is forced to resort to an overly conservative
design style, (known as guardbanding) which, in turn, reduces chip performance as well as running the risk
of early chip failures in the field. Also, by doing more complete reliability assessments, a designer can
avoid problems that in the past may only have been found during chip burn-in. Avoiding a problem earlier is
extremely valuable, considering the chip tooling costs to do a re-spin and the time to market impacts of
finding problems so much later in the design cycle.
About Celestry Reliability Solutions
Celestry provides software and silicon measurement services that have been addressing reliability concerns
for years. Prior customers have been select niche applications that have ultra high reliability needs.
However, today, now that 0.13 micron processes are a reality, high performance IC design teams must consider
addressing the degradation of performance with realistic design budgets to avoid the potential reduced
reliability in a manner such that product life is not too short and to avoid problems previously only found
during burn-in.
RelXpert (formerly called BTABERTTM) is the industry standard SPICE level hot-carrier simulator.
It can precisely simulate circuit performance change due to device HCI degradation, thus ensuring
robust and high performance designs on 0.18-micron technologies and below. RelXpert has been enhanced
to provide NBTI degradation. Designers are able to simultaneously evaluate the trade-offs between higher
performance and reduced design margins. In the end, the best possible combination of speed and immunity
to adverse hot-carrier effects can be achieved. Through the implementation of NBTI and hot-carrier simulation
strategies, designers can develop more aggressive and higher-performance products by using RelXpert.
RelPro+ extracts the parameters needed to do HCI & NBTI modeling and simulation.
DeltaMOS is a new compact device model option for RelPro+ from Celestry for modeling HCI degradation.
It is available now and offered as an option to Celestry's RelPro+ and RelXpert.
For more information on Celestry and solutions available, please go to www.celestry.com.