Now that IC geometries have gone to .25 micron and below, designers must focus on interconnect delay and signal integrity issues. For achieving timing closure, it has become imperative to capture accurate coupling noise with a powerful full-chip 3D extraction tool.
Nautilus, from Celestry provides the ideal solution for high capacity, full-chip 3D parasitic extraction and delay analysis. Nautilus meets the capacity and accuracy requirements for .25 micron and below designs. Celestry has pioneered a series of innovative technologies to create a powerful tool that serves as a critical link between the layout and timing in a cell-based design flow.
Many extraction tools unduly tax the memory capacities of computer platforms and consequently fail to produce usable results. With highly complex designs, engineering environments often must perform extraction on multiple computers.
Anticipating an explosion in data sizes, Celestry has designed Nautilus to eliminate the memory bottlenecks that occur when working on multi-million cell designs. Running on a single CPU, Nautilus achieves an overnight turnaround time for one-million plus cells. With a distributed processing configuration, run-times can be reduced to just hours -- even for the largest designs.
Many extraction tools validate the accuracy of extraction results using average error. However, at .25 micron and below, the tighter timing constraints no longer tolerate corner cases in which accuracy may be sacrificed by 50% or more.
Bounded error is the only measure that provides the confidence designers need. To minimize boundary effects, Nautilus achieves bounded error by using an interconnect library-based approach in combination with our unique Smart Cutting technology.
A major source of extraction error is due to boundary effects caused by cutting nets into small segments. In contrast to other geometrical primitive based approaches, Nautilus uses a Smart Cutting technology in conjunction with the 3D interconnect library to control the decomposition error. The cutting is based on the 3D electrical field distribution. Boundary effects are minimized.
Two approaches are primarily used for extraction: library-based and rule-based (or closed- formula-based). Rule-based extraction (also referred to as analytical extraction) uses a set of closed-form formula for different geometric configurations. Coefficients of the formula are determined based on different ranges of physical parameters such as widths and spacings between wires. For cases where the geometries fall inside the valid range of coefficients this approach may be effective. However, a trio of problems result.
With the library-based approach used by Nautilus, a rich set of predefined libraries are characterized using a 3D field solver. During the on-line extraction, those libraries are matched in real environments and the characterized field solver results are invoked. This approach provides the most accurate parasitics because all capacitance values are based on a 3D field solver in a real 3D environment. This approach is far more robust and guarantees accuracy when processes migrate to smaller feature sizes. All results come directly from field solver, so the error is guaranteed to be bounded within a certain range and is very predictable.
Nautilus supports industry-standard data formats, providing seamless integration into most cell-based design flows.
Nautilus incorporates the industry's leading delay calculation engine which achieves accuracy very close to SPICE results. It calculates delays for both cells and interconnects in multi-million cell designs at unparalleled speed. Combining high capacity, 3D extraction and high accuracy delay calculation, Nautilus provides designers the critical link between layout and timing.
