Nautilus DC

Full-chip delay analysis for timing sign-off

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Timing closure is critical in DSM design, especially at 0.25 micron or below. Timing problems, such as interconnect delay and clock skew, must be eliminated before costly fabrication processes begin. However, full-chip timing verification requires more than RC extraction. Huge amounts of RC data must be analyzed accurately and efficiently.

Nautilus DC, from Celestry, is the most accurate cell level SOC/ASIC design sign-off timing calculation solution. An industry-leading delay analysis tool, Nautilus DC computes highly accurate cell and interconnect delays. Today, many leading semiconductor companies count on Nautilus DC to perfect the timing of their most advanced ICs.

Nautilus DC delivers benefits for timing-critical designs

Accurate analysis for timing closure




By performing thorough timing verification, timing problems can be eliminated prior to tape-out. However, most static timing analysis tools were not designed to accurately analyze the interconnect effects and are unable to handle the large volume of RC data. Nautilus DC complements static timing analyzers by providing them with highly accurate cell and interconnect delays. To help reduce design iterations, Nautilus DC can also feed delay data and constraints to synthesis and place and route tools.

High speed S-parameter interconnect modeling

Nautilus DC incorporates some revolutionary technologies to achieve accuracy very close to SPICE results. However, it operates orders of magnitude faster than any SPICE or circuit analysis tools. Unlike other interconnect modeling techniques, Nautilus DC employs Scattering-parameter macro-models. The technique achieves much higher accuracy and can handle general interconnect topologies such as 2D, 3D meshes, and capacitor loops.

Advanced signal slope modeling

Traditional delay or timing analysis tools use a single ramp to model the signals. Due to large resistance on the interconnect line, this approach can produce very inaccurate results, especially for designs implemented in sub 0.25 micron processes. Nautilus DC models the signal as either an exponential or a multi-piece slope that closely resembles the real signal waveform.

Capturing driving point waveform with Fast Driver

The common misperception is that interconnect delay dominates gate delay in deep submicron design. However, with the exception of global signals, interconnect delays are generally smaller than cell delays. Rather, it is the intricate interactions between the interconnect network and its driver's driving capability that make the most significant impact on both cell and interconnect delays. Nautilus DC uses a proprietary Fast Driver model to efficiently and precisely capture the signal waveform at the cell's driving point.

Detailed clock skew analysis

Accurate and complete clock skew analysis is essential for timing verification. Typically composed of distributed RC trees and meshes with many stages of buffering, clock networks are usually analyzed with slow, error prone circuit analysis tools such as SPICE.

To rapidly isolate clocking issues without the need for circuit simulations, Nautilus DC computes the worst and best-case insertion delays and clock skews. The tool generates detailed clock skew reports. An easy-to-use graphical interface shows the locations of clock pins with color-coded delay values. Users can isolate problematic clock pins and quickly fix the problems.

Critical path SPICE deck generation

After identifying critical paths with static timing analysis, designers often run SPICE simulation to determine the exact delays. Nautilus DC provides a feature that will generate SPICE decks for a given set of critical paths. The SPICE deck includes the netlist of the critical path as well as the appropriate slopes at the primary inputs. Nautilus DC will also perform Boolean analysis and tie-off the input pins of each gate to the appropriate logic "0" or "1", thereby guaranteeing the SPICE simulation will execute a true logic path and find the real delays.


Hierarchical, mixed pre-layout, post-placement and post-layout delay analysis

Because designs are increasingly assembled and verified at the block level, Nautilus DC supports block or IP core-based design methodologies. Nautilus DC can stitch together hierarchical, multiple DSPF files so designers don't have to repeat full-chip extraction every time they perform changes within a block. Designers can also verify any design changes or newly designed logic by using a Verilog or VHDL netlist together with other extracted blocks. Full-chip delay analysis can be performed without full-chip extraction and even before layout is completed.

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